The present invention generally relates to a display. More particularly, the present invention relates to a liquid crystal display having double layer structured transparent pixel electrodes and thereby showing high aperture ratio. The present invention also provides a method for manufacturing the same.
In many applications, liquid crystal displays("LCDs") have replaced cathode ray tubes, which are commonly known as "CRTs" for a variety of reasons. In particular, LCDs are much thinner and generally lighter in weight than conventional CRTs. More wide applications using LCDs are desiring a variety of features such as making the panel size larger, enhancing transmittance of incident light, enhancing contrast ratio, widening viewing angle, and reducing response time.
There are provided three methods for enhancing transmittance of incident light. First is improving aperture ratio, second is use of a polarizing plate with high transmittance, and third is use of a color filter with high transmittance. Among these three methods, the first method of improving aperture ratio is most widely used.
FIG. 1 shows a conventional liquid crystal display having a thin film transistor as a switching element for switching data signals applied to a pixel electrode.
Referring to FIG. 1, there is provided a transparent insulating substrate 1. Although not shown in the drawing, another transparent insulating substrate confronts the transparent insulating substrate 1 with a liquid crystal layer intervening therebetween. A gate bus line 10 and a data bus line 20 are arranged on inner surface of the transparent insulating substrate 1, and the lines 10 and 20 are orthogonal to each other. On the crossing point of the lines 10 and 20, there is provided a thin film transistor 30. The thin film transistor 30 includes a gate electrode 31 extended from the gate bus line 10, a source electrode 36 extended from the data bus line 20, a drain electrode 37 apart by a selected distance from the source electrode 36, and a channel layer 33 acting as a path for carrier transmission from the source electrode 36 to the drain electrode 37, or vice versa. Here, a unit pixel region is defined as a region bounded by the gate bus line 10 and the data bus line 20. A transparent pixel electrode 40 is formed within the unit pixel region. The transparent pixel electrode 40 is spaced apart by a selected distance from the gate bus line 10, and the data bus line 20. The transparent pixel electrode 40 is connected to the drain electrode 37 of the thin film transistor 30. A storage electrode 31b is arranged parallel with the gate bus line 10, and is disposed between a pair of gate bus lines.
FIG. 2 is a simplified sectional view taken along a line 202-202' of FIG. 1. Referring to FIG. 2, the gate electrode 31a is disposed over the transparent insulating substrate 1 on which a first insulating layer 2 is formed. A second insulating layer or gate insulating layer 32 is formed on entire surface of a first resultant substrate on which the first insulating layer 2 and the gate electrode 31a are formed. On a selected portion of upper surface of the gate insulating layer 32 is disposed a semiconductor layer 33 acting as the channel layer. An etch stopper for preventing etch of the semiconductor layer 33 is provided on a selected portion of upper surface of the semiconductor layer 33, and protects the underlying semiconductor layer 33 from-external environment. The source electrode 36 and the drain electrode 37 are disposed on the semiconductor layer 33. Between the source electrode 36 and the semiconductor layer 33 and between the drain electrode 37 and the semiconductor layer 33 is disposed an ohmic contact layer 35 of doped amorphous silicon for ohmic contact with the source and drain electrodes 36 and 37.
FIG. 3 is a simplified sectional view taken along a line 203-203' of FIG. 1. Referring to FIG. 3 and FIG. 1, the storage electrode 31b forms a storage capacitor 50 with the overlying transparent pixel electrode 40 and the gate insulating layer 32 sandwiched therebetween.
Returning to FIG. 1, the separation between the transparent pixel electrode 40 and the data bus line 20 adjacent thereto is to prevent horizontal crosstalk between them. With such a structure, however, it is often difficult to sufficiently secure both of storage capacitance and aperture ratio. So as to remove such limitation, there is provided an overlapping structure which the transparent pixel electrode 40 overlaps with the data bus line 20 as shown by dotted lines of FIG. 1. The overlapping structure makes it possible to obtain high aperture ratio of 80% or more, but it still has a shortcoming such as vertical crosstalk between overlapping portion of the transparent pixel electrode 40 and the data bus line 20. In addition, there is further provided a structure which uses a material having a comparatively low dielectric constant as the insulating layer disposed between them, but the structure has a shortcoming to decrease the storage capacitance.